1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to efficiently allocating data in a memory hierarchy.
2. Description of the Relevant Art
Lower-level memory in a computing system, such as off-chip dynamic random access memory (DRAM) and hard drives, provides relatively inexpensive data storage compared to on-chip caches. However, when servicing data access requests for one or more software applications, the access times of lower-level memory may be appreciable and impact system performance.
One approach to improving performance involves using one or more caches to reduce data access latencies. While using caches can improve performance, various issues may reduce the effectiveness of cache performance. For example, conflict, or collision, misses occur within a set-associative or a direct-mapped cache when too many blocks map to a same set. The misses cause one or more blocks to be discarded within that set. As a consequence, the average memory latency for a given source in the system may be degraded due to the misses. This problem may become worse when two or more sources use the cache for data storage. For example, a video subsystem in a computing system may include multiple sources for video data. The design of a smartphone or computer tablet may include user interface layers, cameras, and video sources such as media players. Each of these sources may utilize video data stored in memory. If each of these sources attempts to store respective data in the cache, both the conflict misses and the frequency of data eviction may increase and thereby cause a reduction in overall system performance. Additionally, power consumption may increase due to such evictions. Further, logic for replacement algorithms and queues used to send evicted data to lower-level memory may consume additional power.
In view of the above, methods and mechanisms for efficiently allocating data in a memory hierarchy are desired.